Technical Specifications
Fusion electronics extension.
Trace impedance and layer stackup are calculated.
Signal reflection analysis is performed in the time domain.
Interference between adjacent traces is evaluated.
All critical nets are scanned in a single operation.
Rule violations are marked on the layout.
Requires a Fusion subscription.
Offered as an annual or multi-year subscription.
Key Features
Early Error Detection
High-speed design errors are caught before prototyping.
In-Layout Analysis
Analysis is performed directly in the layout environment.
No Separate Tool
No separate simulation tool is needed.
